World’s first AV1 decoder silicon IP with support for 12-bit pixel size and 4:4:4 chroma sub-sampling released by Allegro DVT
Allegro DVT, the leading provider of video processing silicon IPs and video compliance streams, has announced that its D310 AV1 Decoder silicon IP now supports 12-bit sample size and 4:4:4 chroma sub-sampling. Emerging applications such as cloud-gaming, automotive and screen mirroring will directedly benefit from these new features to provide a superior video quality and preserve the finest details in video content.
Allegro DVT’s D310 IP is part of the D3x0 highly customizable silicon IP family that builds on a scalable architecture allowing picture resolutions ranging from HD/4K up to 8K/16K while providing support for sample sizes from 8-bit to 12-bit and chroma subsampling from 4:0:0 up to 4:4:4.
Allegro DVT is able to address the growing demand of state-of-the-art video processing blocks in advanced System-on-Chips (SoCs) by providing highly configurable decoding IP cores supporting a variety of selectable codecs. In addition to AV1, the D3x0 family also supports JPEG, H.264, HEVC, VP9 and VVC video formats. Furthermore, its unique and scalable architecture approach offers the best trade-off between silicon size and power consumption keeping the operating frequency of the resulting solutions at a reasonable level to allow physical implementations in mainstream and cost-efficient process node technologies.
The D310 is immediately available with a comprehensive documentation and SW drivers for a smooth integration into video SoCs.
Nouar Hamze, CEO, commented “We are committed to supporting the AV1 ecosystem and accelerating the adoption of this promising video codec. Our D310 product is the very first AV1 Decoder IP to provide support for 12-bit pixel size and 4:4:4 chroma subsampling format. These high-end features will extend the breadth of target applications to includes advanced HDR, cloud-gaming, wireless display and automotive in which preserving video quality is of utmost importance. This IP represents the culmination of our engineering and marketing effort in bringing together the requirements of vastly different applications and generating optimal solutions in terms of power, performance, and area.” Business Wire
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