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Govt has Rs100cr budget for chip design related activities this fiscal: Vaishnaw

Electronics and IT Minister Ashwini Vaishnaw informed the Rajya Sabha in a written reply that semiconductor design is a highly knowledge-intensive field and needs exceptionally skilled manpower and tools.

He said India has a huge talent pool for semiconductor design and a high number of design patents and intellectual property rights (IPR) are produced in the country by design engineers.

“The total budget allocation for chip design related activities / programmes in the current financial year is Rs 100 crore,” Vaishnaw said.

He said that the government is focused on broadening and deepening the Electronics System Design and Manufacturing (ESDM) sector with semiconductor design as one of the focus areas.

Currently, semiconductor wafer fabrication facilities for strategic requirements are available at SemiConductor Laboratory (SCL), Mohali; Gallium Arsenide Enabling Technology Centre (GAETEC), Hyderabad and Society for Integrated Circuit Technology and Applied Research (SITAR), Bengaluru, the minister said.

To push development of semiconductors, the government has approved ‘Establishment of Gallium Nitride (GaN) Ecosystem Enabling Centre and Incubator for High Power and High Frequency Electronics’.

The project is being implemented by Society for Innovation and Development (SID) under the auspices of Indian Institute of Science (IISc) at Centre for Nano Science and Engineering (CeNSE), Bengaluru at the total project cost of Rs 298.66 crore.

“An application for setting up of Assembly, Testing, Marking and Packaging (ATMP) of NAND Flash memory has been approved under the Production Linked Incentive (PLI) Scheme for large scale electronics manufacturing,” Vaishnaw said.

He said that an application for discrete semiconductor devices, including transistors, diodes, thyristors, etc. and System in Package (SIP) has been approved under the PLI Scheme for large scale electronics manufacturing. Outlook India

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